The invention relates generally to disk drive systems, and more particularly, to a processing mechanism for transferring data between a fibre channel and the cache memory of a disk drive controller.
Disk drive systems have grown enormously in both size and sophistication in recent years. These systems typically include many large disk drive units controlled by a complex multi-tasking disk drive controller such as the EMC Symmetrix disk drive controller. A large scale disk drive system can typically receive commands from a number of host computers and can control a large number of disk drive mass storage elements, each mass storage element being capable of storing in excess of several gigabits of data. There is every reason to believe that both the sophistication and size of the disk drive systems, and the controllers contained within them, will continue to increase.
As the systems grow, and become faster, the demands for moving data within the disk drive controller increase. Not only are these demands upon the disk drive controller to increase data throughput, but in addition, there are requirements for improving the quality of the data passed through the system, that is, to provide for necessary error checking, and reliability as the flow of data increases substantially.
In accordance with the invention, therefore, there is advantageously provided an increased flow rate system for moving data between the large cache memory of a Symmetrix disk drive system controller and the fibre of a high data rate fibre channel which can feed data, to, or take data from, the controller. The invention also provides for a reliable and flexibly controllable data path through which the data passes.
The invention relates to a method and apparatus for connecting between a serial fibre channel link and a global memory. The apparatus features a bidirectional physical interface for terminating the fibre channel link at a first port and an electrical interface signal at a second port; a bidirectional conversion circuitry connected to the second port for connecting between the electrical interface signal and a high bandwidth data signal, for example, a PCI data signal; a bidirectional lower machine connected to a CPU bus for connecting between the PCI data signal and a multi-pipe input/output signal; an error detection and correction circuitry for converting between the primary input/output signal and a corrected input/output signal; a plurality of dual port random-access-memories for storing the corrected input/output signal and forwarding such corrected input/output signal to a global memory; a secondary port interface connected to a CPU bus and to the conversion circuitry over a secondary port interface bus, for controlling the conversion circuitry; and a second random-access-memory connected to the secondary port interface bus.